JP 2007-336037 A discloses a reset signal control apparatus that is able to reduce an output period of a reset signal when a microprocessor is started. The reset signal control apparatus receives, from the microcomputer, a clock signal based on which the microprocessor operates, and inputs the received clock signal to a reset control circuit as a feedback signal. The reset control circuit outputs a reset signal to the microcomputer with monitoring the clock signal. When the reset control circuit determines that the clock signal becomes stable, the reset control circuit stops an output of the reset signal after a stabilization period of the microprocessor has elapsed.
However, in the above-described reset signal control apparatus, the microprocessor needs a terminal for outputting the clock signal to the reset signal control apparatus, and the reset signal control apparatus needs a terminal for receiving the clock signal from the microcomputer. Thus, both a quantity of the terminals in the microprocessor and a quantity of the terminals in the reset control circuit increase, and accordingly, a cost and a size of the reset signal control apparatus is increased.